Every hardware design contains architectural decisions that profoundly affect the final product’s power, performance, and area. Most teams make these decisions early with limited data, and live with the consequences through tapeout. Evaluating architectural alternatives at RTL can take hours if not days per iteration, making meaningful exploration impractical on real project schedules. Rise changes this by running the closed loop at the high level where synthesis completes in seconds, enabling teams to generate and evaluate tens to hundreds of design candidates with correlated PPA feedback before committing to an architecture.

The Rise Optimization Agent uses algorithmic parameter search and learned predictions to converge toward an optimal Pareto front across any combination of metrics including pipeline depth, memory hierarchy, parallelism, area, latency, power, and timing closure. Rather than manual parameter sweeps, the system runs targeted trials and refines based on user-set goals and constraints, with full analysis, debug, and compare visibility at every step.

The flow is designed to be extended with higher fidelity estimation as needed. In one example, Rise integrated with hls4ml to take ML models directly from Keras, TensorFlow, or PyTorch through the full synthesis and verification loop, with the Optimization Agent managing Pareto front analysis across the parameter space. In another, Rise integrated OpenROAD as a plug-in PnR estimation phase, adding physical implementation correlation to the exploration loop and giving teams confidence that the architectures they are selecting will close in silicon.